An IP Core of AMBA Bus Interface in HDL

The AMBA on-chip bus architecture is a well-known open specification that explains how to connect and manage the functional units make up System-On-Chip (SoC). design implementation of an AHB Master, RAM, ROM, FIFO Memory Controller proposed in this paper. It primarily divided into two categories: operation initiator (AHB MASTER) SLAVE. Furthermore, master generate burst mode, single transfer according interface requirement Address generator, generates address increment or wrap as well completing data transfers with asymmetric asynchronous variable widths for read write. A bridge between Master slave will be demonstrated using memory controller, their outcome terms area speed ed. finite state machine used control framework. Xilinx Virtex 2 XC2VP40 implement Slave IP.